In power components, in particular power transistors, having a vertical layout, a first main electrode metallization and the control electrode metallization are formed on a first side (top side) of the semiconductor chip, and the second main electrode metallization is formed on a second side (back side) of the semiconductor chip. Soldering to a connection device or a connection grid—as a rule a substrate or tape (flexible film)—may be done quickly, simply and economically for the larger, second main electrode metallization, for instance a source metallization, with a surface area of 20 mm2 by interposing a large-area solder foil or by a solder paste imprint onto the connection grid. The control electrode metallization is embodied as very small, with a surface area of 1 mm2 or less, for instance. To assure adequate positioning precision in the solder coating, the solder must therefore at least be applied to the patterned front side of the semiconductor chip in advance, in an additional laborious, complex and expensive process step in the form of solder bumps. After that, the connection devices are soldered to the semiconductor chip incorporated between them in a soldering oven.
A plurality of semiconductor chips may be placed laterally next to one another and soldered between common connection devices. U.S. Pat. No. 6,072,240 discusses one such semiconductor component and the method for its production, in which transistors in reverse arrangement are soldered between common substrates.
The semiconductor component of the present invention and the exemplary method of the present invention by comparison have the advantage in particular that relatively simple, fast and nevertheless reliable production of the semiconductor component is made possible. By embodying an insulation layer and additional metal layers or metal planes on the front side of the semiconductor chip, it is possible to dispense with the additional step of applying solder bumps. According to one embodiment, in particular, a semiconductor component configuration including at least one semiconductor component of the exemplary embodiment and/or exemplary method of the present invention and at least one connection device soldered to it is created.
According to the exemplary embodiment and/or exemplary method of the present invention, on the first side of the semiconductor chip an insulation layer that partially covers the lower, first main electrode layer—already used in conventional components—is thus applied between the first main electrode layer and the gate electrode layer. Next, according to the exemplary embodiment and/or exemplary method of the present invention, upper electrode layers or metal planes are applied to the lower electrode layers of the first side; the upper control electrode layer or gate electrode layer may be embodied with a substantially larger area than the lower control electrode layer, by forming it over a larger region of the insulation layer, and in particular even above the overlapped region of the lower, first main electrode layer. Thus with the embodiment of a suitable insulation layer, a desired dimensioning of the upper electrode layers or upper metal planes, which have a larger area for the solder to be applied, is attainable. As a result, the solder—as is also true on the second side or underside of the semiconductor chip—may be provided using an interposed solder foil or by a solder paste applied, for instance imprinted, onto the connection device.
The resultant graduations in the electrode layers, in particular inside the upper control electrode layer as well, are in principle already evened out by the solder that melts out in the assembly process; in addition, a supplementary method for planarizing the chip surfaces may be performed, for instance by partial insertion of one or more intermediate oxide layers.
Both ceramic substrates and flexible films or tapes, having suitably dimensioned conductive terminal regions, may be used as the connection device or connection grid. In particular, one or two DBC (direct bonded copper) substrates, which include(s) one further metal layer on the outside of the component formed according to the exemplary embodiment and/or exemplary method of the present invention, may be used.
According to the exemplary embodiment and/or exemplary method of the present invention, in particular, two or more semiconductor chips side by side may be soldered between two connection devices. For instance, two or more transistors may be soldered in reverse disposition, allowing for the formation of a contacting or connection of the electrodes of the transistors by the conductive terminal regions on the connection devices.
According to the exemplary embodiment and/or exemplary method of the present invention, not only field effect transistors may be created but also other semiconductor components, such as bipolar transistors or thyristors.